The present invention relates to an interleave memory control apparatus and method. In particular, the present invention relates to a memory control apparatus and method for controlling an interleave of a memory.
A dynamic random access memory (DRAM) is often used for a memory device in an information processing system. A DRAM generally requires, after it is accessed, a waiting time of several tens of nano-seconds (ns) until the next access can be made. Based on this, there has been introduced, in high performance systems, an interleave system to minimize the DRAM waiting time. In the interleave system, an address is exclusively given to an aggregation of a plurality of DRAMs (hereinafter, called a bank) that may be accessed in parallel. In this case, if the object bank is different, a new access may be made in parallel to another bank without waiting for the end of access of the object bank during execution. The bank addresses are often given so that different banks are sequentially used when the addresses to the memory are continuous, which utilizes the characteristic that continuous access to the memory is executed in an ascending or descending sequence.
On the other hand, since memory capacity required for an information processing system is different depending on users, needs or the processing object, the memory capacity may be varied in many information processing systems. Therefore, users are capable of selecting adequate memory capacity within the range between a minimum capacity and a maximum capacity of the information processing system, and expanding the memory capacity at a later time, depending on the memory requirements. In view of realizing such a requirement, a memory device may be composed of a loading unit called a memory module. When one memory module forms one bank, it may be considered that a plurality of banks are included in one memory module and one bank is formed of a plurality of memory modules. Moreover, in some cases, only a kind of memory module is provided, but it is also probable that a large capacity memory module may be provided because of a generation change of a DRAM.
If a memory module of different capacity is provided, it is important for protection of hardware resources of users to allow for the use of a new large capacity module in combination with an old small capacity module. In order to allow co-existence of memory modules having different capacities, it is required to introduce a method of supplying addresses without any problem to various combinations of different memory modules. Moreover, another method can also be considered, in which the continuous addresses starting from the maximum address before expansion are given to the memory modules expanded. In this case, since the interleave in the added address regions is executed within the expanded memory modules, the expanded memory modules are required to have the sufficient number of banks. However, since the depth in the address direction increases for the bit width with increase of capacity of a DRAM, the memory capacity increases in the memory modules having a plurality of banks. Thereby, it is impractical to provide memory modules of a small expansion unit.
Therefore, in view of keeping small the expansion unit and acquiring a high multiplexing degree of interleaving (interleaving factor, or number of way), it is required to provide an interleave that is variable depending on the structure of memory device and memory module, and also provide an interleave that is variable for the expansion modules and those already provided.
As a method of realizing the interleave, it is considered to form an interleave by combining the banks of equal capacity as shown in FIG. 7. For example, it is assumed that the bank of No. %0 and No. %1 each has a capacity of 4 MB, the bank of No. %2 and %3 each has a capacity of 2 MB, and the bank of No. %4 to %7 each has a capacity of 1 MB. In this example, a two-way interleave is formed with 8 MB total capacity with bank No. %0 and %1, a two-way interleave is also formed with 4 MB total capacity with bank No. %2 and %3, and a four-way interleave is formed with 4 MB total capacity with bank No. %4 to %7.
As another method, for example, it is also considered that a plurality of banks having a small capacity are combined to form banks having a large capacity, as shown in FIG. 8. When the banks are assumed to have the capacity like that of FIG. 7, a four-way interleave can be formed with a total capacity of 16 MB.
In the above technique, for example, when the weighted mean of the multiplexing degree of interleaving (interleaving factor) is calculated in the example shown in FIG. 7, it can be obtained as EQU (2 WAY.times.8 MB+2 WAY.times.4 MB+4 WAY.times.4 MB)/16 MB=2.5
and the 2.5-way interleave can be formed substantially. Meanwhile, in the example of FIG. 8, it can be understood that the four-way interleave is formed, and the multiplexing degree is obtained as EQU (4 WAY.times.16 MB)/16 MB 4.0
In these techniques, the multiplexing degree of interleave is limited, and thereby memory performance is deteriorated. Namely, the throughput of memory is lowered if an interleave that cannot substantially utilize the natural parallelism is structured in spite of having a bank provided in a physically different slot.